搜索资源列表
DDS
- 这个是我自己用VHDL语言写的两相数字信号发生器程序 D/A用的是DAC904-This is for my own use VHDL, written procedures for two-phase digital signal generator D/A using a DAC904
Verilogexample
- verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci
sin
- QUARTUSS||环境下的简易正弦信号发生器的设计，VERILOG 代码，用到了嵌入式逻辑分析仪-QUARTUSS | | environment simple sinusoidal signal generator, VERILOG code, use the embedded logic analyzer
crc-gen
- CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
viterbi
- This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
Verilog
- ：Verilog实现的DDS正弦信号发生器和测频测相模块-: Verilog implementation of the DDS sine signal generator and frequency measurement module test phase
DDS__FPGA
- 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容
DDS
- Verilog语言实现基于DDS技术的余弦信号发生器，输出位宽16Bit-Verilog language technology based on the cosine DDS signal generator, the output bit width 16Bit
prbs
- 伪随机二进制序列发生器的Verilog源码，带测试文件，并在FPGA开发板上成功验证-Pseudo-random binary sequence generator Verilog source code, with a test file, and successfully verified in FPGA development board
hd_source
- 基于Verilog HDL的视频测试pattern发生器。内置各种常见模式。-Verilog HDL-based video test pattern generator. Built-in a variety of common models.
waveform
- Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形-Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform
verilog
- 波形发生器，产生4种波形，能够自己手动转换，并能调节输出频率-Waveform generator to produce four kinds of waveforms that can convert your manual, and can adjust the output frequency
54088960verilog_multicrc
- CRC校验码生成器的程序编码，verilog编写-The CRC generator to the program code, verilog write
5B6B-codec
- verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, d
Verilog-Mxulie
- 用Verilog编的M序列代码，用的是移位发生器的思想，即循环移动并用后来的数值取代-M-sequence code in Verilog code, using the shift generator the idea that the circulation moving and replaced with the later values
UART_verilog
- 带波特率发生器的FPGA_UART串口通信代码，使用ISE10.1综合应用过，通过计算调整两个参数baud_frequcy,baud_limit可适用于多种波特率下的UART传输-With a baud rate generator FPGA_UART serial communication code, use ISE10.1 integrated application before, by calculating the adjusted two parameters baud_frequ
DDS-VERILOG
- DDS的信号发生器verilog代码 可直接用于编程 已经测试-Verilog code of the DDS signal generator which can be used directly in the programming has been tested
verilog_sine-wave-generator
- verilog语言书写的基于DDS相频累加器的正弦波发生器-verilog language of the sine wave generator
signal-generator
- Design of DDS signal generator based on VHDL+FPGA, has been through the adjustable, can be directly used, simulation -DDS signal generator circuit design, Verilog source code, can be directly used, simulation
Verilog_HDLsequence-generator
- Verilog序列产生器，内有代码，可产生随机序列-Verilog sequence generator, which have code that generates random sequences